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<table class="code" id="codeTbl">
<tr name="1" id="1">
<td><a id="l1" class='ln'>1</a></td><td><span class="ct">/*</span></td></tr>
<tr name="2" id="2">
<td><a id="l2" class='ln'>2</a></td><td><span class="ct"> * Code generated for Simulink model VCUComposition_demo.</span></td></tr>
<tr name="3" id="3">
<td><a id="l3" class='ln'>3</a></td><td><span class="ct"> *</span></td></tr>
<tr name="4" id="4">
<td><a id="l4" class='ln'>4</a></td><td><span class="ct"> * FILE    : spi.c</span></td></tr>
<tr name="5" id="5">
<td><a id="l5" class='ln'>5</a></td><td><span class="ct"> *</span></td></tr>
<tr name="6" id="6">
<td><a id="l6" class='ln'>6</a></td><td><span class="ct"> * VERSION : 1.86</span></td></tr>
<tr name="7" id="7">
<td><a id="l7" class='ln'>7</a></td><td><span class="ct"> *</span></td></tr>
<tr name="8" id="8">
<td><a id="l8" class='ln'>8</a></td><td><span class="ct"> * DATE    : Sun Sep  8 01:03:14 2024</span></td></tr>
<tr name="9" id="9">
<td><a id="l9" class='ln'>9</a></td><td><span class="ct"> *</span></td></tr>
<tr name="10" id="10">
<td><a id="l10" class='ln'>10</a></td><td><span class="ct"> * Copyright 2011-2017 ECUCoder. All Rights Reserved.</span></td></tr>
<tr name="11" id="11">
<td><a id="l11" class='ln'>11</a></td><td><span class="ct"> */</span></td></tr>
<tr name="12" id="12">
<td><a id="l12" class='ln'>12</a></td><td></td></tr>
<tr name="13" id="13">
<td><a id="l13" class='ln'>13</a></td><td><span class="pp">#include "spi.h"</span></td></tr>
<tr name="14" id="14">
<td><a id="l14" class='ln'>14</a></td><td><span class="pp">#if</span> (<a id="14c6" class="tk">SPIAENABLE</a><a id="14c16" class="tk">||</a><a id="14c18" class="tk">SPIBENABLE</a>)</td></tr>
<tr name="15" id="15">
<td><a id="l15" class='ln'>15</a></td><td></td></tr>
<tr name="16" id="16">
<td><a id="l16" class='ln'>16</a></td><td><span class="ct">/**************************************************************************</span></td></tr>
<tr name="17" id="17">
<td><a id="l17" class='ln'>17</a></td><td><span class="ct"> * FUNCTION :    ec_spi_delay                                              *</span></td></tr>
<tr name="18" id="18">
<td><a id="l18" class='ln'>18</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="19" id="19">
<td><a id="l19" class='ln'>19</a></td><td><span class="ct"> * DESCRIPTION : A delay function. Wait until get RFDF flag                *</span></td></tr>
<tr name="20" id="20">
<td><a id="l20" class='ln'>20</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="21" id="21">
<td><a id="l21" class='ln'>21</a></td><td><span class="ct"> * PARAMETERS :  -DSPIn: can be DSPI0, or DSPI1                 *</span></td></tr>
<tr name="22" id="22">
<td><a id="l22" class='ln'>22</a></td><td><span class="ct"> *               -us: the number of us to be delayed                       *</span></td></tr>
<tr name="23" id="23">
<td><a id="l23" class='ln'>23</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="24" id="24">
<td><a id="l24" class='ln'>24</a></td><td><span class="ct"> * RETURN :      None                                                      *</span></td></tr>
<tr name="25" id="25">
<td><a id="l25" class='ln'>25</a></td><td><span class="ct"> ***************************************************************************/</span></td></tr>
<tr name="26" id="26">
<td><a id="l26" class='ln'>26</a></td><td><span class="kw">void</span> <a id="26c6" class="tk">ec_spi_delay</a>(<a id="26c19" class="tk">uint8</a> <a id="26c25" class="tk">DSPIn</a>,<a id="26c31" class="tk">uint32</a> <a id="26c38" class="tk">us</a>)</td></tr>
<tr name="27" id="27">
<td><a id="l27" class='ln'>27</a></td><td><span class="br">{</span></td></tr>
<tr name="28" id="28">
<td><a id="l28" class='ln'>28</a></td><td>  <a id="28c3" class="tk">uint32</a> <a id="28c10" class="tk">i</a>,<a id="28c12" class="tk">j</a>;</td></tr>
<tr name="29" id="29">
<td><a id="l29" class='ln'>29</a></td><td>  <span class="kw">for</span> (<a id="29c8" class="tk">i</a>=0; <a id="29c13" class="tk">i</a><a id="29c14" class="tk">&lt;</a><a id="29c15" class="tk">us</a>; <a id="29c19" class="tk">i</a><a id="29c20" class="tk">++</a>) <span class="br">{</span></td></tr>
<tr name="30" id="30">
<td><a id="l30" class='ln'>30</a></td><td>    <span class="kw">for</span> (<a id="30c10" class="tk">j</a>=0; <a id="30c15" class="tk">j</a><a id="30c16" class="tk">&lt;</a>20; <a id="30c21" class="tk">j</a><a id="30c22" class="tk">++</a>) <span class="br">{</span></td></tr>
<tr name="31" id="31">
<td><a id="l31" class='ln'>31</a></td><td>      <span class="kw">if</span> (1 <a id="31c13" class="tk">==</a> <a id="31c16" class="tk">DSPI</a>(<a id="31c21" class="tk">DSPIn</a>).<a id="31c28" class="tk">SR</a>.<a id="31c31" class="tk">B</a>.<a id="31c33" class="tk">RFDF</a>) <span class="br">{</span></td></tr>
<tr name="32" id="32">
<td><a id="l32" class='ln'>32</a></td><td>        <a id="32c9" class="tk">i</a> = <a id="32c13" class="tk">us</a><a id="32c15" class="tk">+</a>1;</td></tr>
<tr name="33" id="33">
<td><a id="l33" class='ln'>33</a></td><td>        <a id="33c9" class="tk">j</a> = 21;</td></tr>
<tr name="34" id="34">
<td><a id="l34" class='ln'>34</a></td><td>      <span class="br">}</span></td></tr>
<tr name="35" id="35">
<td><a id="l35" class='ln'>35</a></td><td>    <span class="br">}</span></td></tr>
<tr name="36" id="36">
<td><a id="l36" class='ln'>36</a></td><td>  <span class="br">}</span></td></tr>
<tr name="37" id="37">
<td><a id="l37" class='ln'>37</a></td><td><span class="br">}</span></td></tr>
<tr name="38" id="38">
<td><a id="l38" class='ln'>38</a></td><td></td></tr>
<tr name="39" id="39">
<td><a id="l39" class='ln'>39</a></td><td><span class="pp">#endif</span></td></tr>
<tr name="40" id="40">
<td><a id="l40" class='ln'>40</a></td><td></td></tr>
<tr name="41" id="41">
<td><a id="l41" class='ln'>41</a></td><td><span class="pp">#if</span> 1</td></tr>
<tr name="42" id="42">
<td><a id="l42" class='ln'>42</a></td><td></td></tr>
<tr name="43" id="43">
<td><a id="l43" class='ln'>43</a></td><td><span class="ct">/**************************************************************************</span></td></tr>
<tr name="44" id="44">
<td><a id="l44" class='ln'>44</a></td><td><span class="ct"> * FUNCTION :    ec_spi0_init                                              *</span></td></tr>
<tr name="45" id="45">
<td><a id="l45" class='ln'>45</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="46" id="46">
<td><a id="l46" class='ln'>46</a></td><td><span class="ct"> * DESCRIPTION : Initialize DSPI0 module                                   *</span></td></tr>
<tr name="47" id="47">
<td><a id="l47" class='ln'>47</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="48" id="48">
<td><a id="l48" class='ln'>48</a></td><td><span class="ct"> * PARAMETERS :  None                                                      *</span></td></tr>
<tr name="49" id="49">
<td><a id="l49" class='ln'>49</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="50" id="50">
<td><a id="l50" class='ln'>50</a></td><td><span class="ct"> * RETURN:       None                                                      *</span></td></tr>
<tr name="51" id="51">
<td><a id="l51" class='ln'>51</a></td><td><span class="ct"> ***************************************************************************/</span></td></tr>
<tr name="52" id="52">
<td><a id="l52" class='ln'>52</a></td><td><span class="kw">void</span> <a id="52c6" class="tk">ec_spi0_init</a>(<span class="kw">void</span>)</td></tr>
<tr name="53" id="53">
<td><a id="l53" class='ln'>53</a></td><td><span class="br">{</span></td></tr>
<tr name="54" id="54">
<td><a id="l54" class='ln'>54</a></td><td>  <a id="54c3" class="tk">DSPI</a>(0).<a id="54c11" class="tk">MCR</a>.<a id="54c15" class="tk">B</a>.<a id="54c17" class="tk">MSTR</a> = 1;              <span class="ct">/* SPI Mode, Master or Slave */</span></td></tr>
<tr name="55" id="55">
<td><a id="l55" class='ln'>55</a></td><td>  <a id="55c3" class="tk">DSPI</a>(0).<a id="55c11" class="tk">MCR</a>.<a id="55c15" class="tk">B</a>.<a id="55c17" class="tk">CONT_SCKE</a> = 0;</td></tr>
<tr name="56" id="56">
<td><a id="l56" class='ln'>56</a></td><td>  <a id="56c3" class="tk">DSPI</a>(0).<a id="56c11" class="tk">MCR</a>.<a id="56c15" class="tk">B</a>.<a id="56c17" class="tk">DCONF</a> = 0;</td></tr>
<tr name="57" id="57">
<td><a id="l57" class='ln'>57</a></td><td>                         <span class="ct">/* Configure DSPI_A in SPI, DSI or CSI configuration */</span></td></tr>
<tr name="58" id="58">
<td><a id="l58" class='ln'>58</a></td><td>  <a id="58c3" class="tk">DSPI</a>(0).<a id="58c11" class="tk">MCR</a>.<a id="58c15" class="tk">B</a>.<a id="58c17" class="tk">PCSIS</a> = 0<a id="58c26" class="tk">b11111111</a>;</td></tr>
<tr name="59" id="59">
<td><a id="l59" class='ln'>59</a></td><td>  <a id="59c3" class="tk">DSPI</a>(0).<a id="59c11" class="tk">MCR</a>.<a id="59c15" class="tk">B</a>.<a id="59c17" class="tk">MDIS</a> = <a id="59c24" class="tk">!</a>1;             <span class="ct">/* SPI Moudle enable */</span></td></tr>
<tr name="60" id="60">
<td><a id="l60" class='ln'>60</a></td><td>  <a id="60c3" class="tk">DSPI</a>(0).<a id="60c11" class="tk">MCR</a>.<a id="60c15" class="tk">B</a>.<a id="60c17" class="tk">HALT</a> = 1;              <span class="ct">/* Stop transfer */</span></td></tr>
<tr name="61" id="61">
<td><a id="l61" class='ln'>61</a></td><td>  <a id="61c3" class="tk">DSPI</a>(0).<a id="61c11" class="tk">MODE</a>.<a id="61c16" class="tk">CTAR</a>[0].<a id="61c24" class="tk">B</a>.<a id="61c26" class="tk">DBR</a> = <a id="61c32" class="tk">DBR0</a>;   <span class="ct">/* Duty cycle is configurable */</span></td></tr>
<tr name="62" id="62">
<td><a id="l62" class='ln'>62</a></td><td>  <a id="62c3" class="tk">DSPI</a>(0).<a id="62c11" class="tk">MODE</a>.<a id="62c16" class="tk">CTAR</a>[0].<a id="62c24" class="tk">B</a>.<a id="62c26" class="tk">FMSZ</a> = 0<a id="62c34" class="tk">b0111</a>;<span class="ct">/* Frame size=8 */</span></td></tr>
<tr name="63" id="63">
<td><a id="l63" class='ln'>63</a></td><td>  <a id="63c3" class="tk">DSPI</a>(0).<a id="63c11" class="tk">MODE</a>.<a id="63c16" class="tk">CTAR</a>[0].<a id="63c24" class="tk">B</a>.<a id="63c26" class="tk">PCSSCK</a> = 0<a id="63c36" class="tk">b01</a>;<span class="ct">/* PCS to SCK delay scaler, 3 */</span></td></tr>
<tr name="64" id="64">
<td><a id="l64" class='ln'>64</a></td><td>  <a id="64c3" class="tk">DSPI</a>(0).<a id="64c11" class="tk">MODE</a>.<a id="64c16" class="tk">CTAR</a>[0].<a id="64c24" class="tk">B</a>.<a id="64c26" class="tk">CSSCK</a> = 0<a id="64c35" class="tk">b0100</a>;<span class="ct">/* PCS to SCK delay scaler, 32 */</span></td></tr>
<tr name="65" id="65">
<td><a id="l65" class='ln'>65</a></td><td>  <a id="65c3" class="tk">DSPI</a>(0).<a id="65c11" class="tk">MODE</a>.<a id="65c16" class="tk">CTAR</a>[0].<a id="65c24" class="tk">B</a>.<a id="65c26" class="tk">ASC</a> = 0<a id="65c33" class="tk">b0100</a>; <span class="ct">/* After SCK delay scaler */</span></td></tr>
<tr name="66" id="66">
<td><a id="l66" class='ln'>66</a></td><td>  <a id="66c3" class="tk">DSPI</a>(0).<a id="66c11" class="tk">MODE</a>.<a id="66c16" class="tk">CTAR</a>[0].<a id="66c24" class="tk">B</a>.<a id="66c26" class="tk">DT</a> = 0<a id="66c32" class="tk">b0100</a>;  <span class="ct">/* Delay after transfer scaler */</span></td></tr>
<tr name="67" id="67">
<td><a id="l67" class='ln'>67</a></td><td>  <a id="67c3" class="tk">DSPI</a>(0).<a id="67c11" class="tk">MODE</a>.<a id="67c16" class="tk">CTAR</a>[0].<a id="67c24" class="tk">B</a>.<a id="67c26" class="tk">CPOL</a> = 0;</td></tr>
<tr name="68" id="68">
<td><a id="l68" class='ln'>68</a></td><td>    <span class="ct">/* Clock polarity, 0 means the inactive state of SCK is low, 1 means high */</span></td></tr>
<tr name="69" id="69">
<td><a id="l69" class='ln'>69</a></td><td>  <a id="69c3" class="tk">DSPI</a>(0).<a id="69c11" class="tk">MODE</a>.<a id="69c16" class="tk">CTAR</a>[0].<a id="69c24" class="tk">B</a>.<a id="69c26" class="tk">CPHA</a> = 1;</td></tr>
<tr name="70" id="70">
<td><a id="l70" class='ln'>70</a></td><td>          <span class="ct">/* Clock phase, 0 means data is captured on the leading edge of SCK */</span></td></tr>
<tr name="71" id="71">
<td><a id="l71" class='ln'>71</a></td><td>  <a id="71c3" class="tk">DSPI</a>(0).<a id="71c11" class="tk">MODE</a>.<a id="71c16" class="tk">CTAR</a>[0].<a id="71c24" class="tk">B</a>.<a id="71c26" class="tk">LSBFE</a> = 0;</td></tr>
<tr name="72" id="72">
<td><a id="l72" class='ln'>72</a></td><td>                              <span class="ct">/* LSB first enable, 0: MSB first; 1: LSB first */</span></td></tr>
<tr name="73" id="73">
<td><a id="l73" class='ln'>73</a></td><td>  <a id="73c3" class="tk">DSPI</a>(0).<a id="73c11" class="tk">MODE</a>.<a id="73c16" class="tk">CTAR</a>[0].<a id="73c24" class="tk">B</a>.<a id="73c26" class="tk">PBR</a> = 0;      <span class="ct">/* Baud rate prescaler */</span></td></tr>
<tr name="74" id="74">
<td><a id="l74" class='ln'>74</a></td><td>  <a id="74c3" class="tk">DSPI</a>(0).<a id="74c11" class="tk">MODE</a>.<a id="74c16" class="tk">CTAR</a>[0].<a id="74c24" class="tk">B</a>.<a id="74c26" class="tk">BR</a> = 4;       <span class="ct">/* Baud rate scaler */</span></td></tr>
<tr name="75" id="75">
<td><a id="l75" class='ln'>75</a></td><td>  <a id="75c3" class="tk">DSPI</a>(0).<a id="75c11" class="tk">MCR</a>.<a id="75c15" class="tk">B</a>.<a id="75c17" class="tk">HALT</a> = 0;              <span class="ct">/* Start transfer */</span></td></tr>
<tr name="76" id="76">
<td><a id="l76" class='ln'>76</a></td><td><span class="br">}</span></td></tr>
<tr name="77" id="77">
<td><a id="l77" class='ln'>77</a></td><td></td></tr>
<tr name="78" id="78">
<td><a id="l78" class='ln'>78</a></td><td><span class="pp">#endif</span></td></tr>
<tr name="79" id="79">
<td><a id="l79" class='ln'>79</a></td><td></td></tr>
<tr name="80" id="80">
<td><a id="l80" class='ln'>80</a></td><td><span class="pp">#if</span> 1</td></tr>
<tr name="81" id="81">
<td><a id="l81" class='ln'>81</a></td><td></td></tr>
<tr name="82" id="82">
<td><a id="l82" class='ln'>82</a></td><td><span class="ct">/**************************************************************************</span></td></tr>
<tr name="83" id="83">
<td><a id="l83" class='ln'>83</a></td><td><span class="ct"> * FUNCTION :    ec_spi1_init                                              *</span></td></tr>
<tr name="84" id="84">
<td><a id="l84" class='ln'>84</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="85" id="85">
<td><a id="l85" class='ln'>85</a></td><td><span class="ct"> * DESCRIPTION : Initialize DSPI1 module                                   *</span></td></tr>
<tr name="86" id="86">
<td><a id="l86" class='ln'>86</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="87" id="87">
<td><a id="l87" class='ln'>87</a></td><td><span class="ct"> * PARAMETERS :  None                                                      *</span></td></tr>
<tr name="88" id="88">
<td><a id="l88" class='ln'>88</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="89" id="89">
<td><a id="l89" class='ln'>89</a></td><td><span class="ct"> * RETURN:       None                                                      *</span></td></tr>
<tr name="90" id="90">
<td><a id="l90" class='ln'>90</a></td><td><span class="ct"> ***************************************************************************/</span></td></tr>
<tr name="91" id="91">
<td><a id="l91" class='ln'>91</a></td><td><span class="kw">void</span> <a id="91c6" class="tk">ec_spi1_init</a>(<span class="kw">void</span>)</td></tr>
<tr name="92" id="92">
<td><a id="l92" class='ln'>92</a></td><td><span class="br">{</span></td></tr>
<tr name="93" id="93">
<td><a id="l93" class='ln'>93</a></td><td>  <a id="93c3" class="tk">DSPI</a>(1).<a id="93c11" class="tk">MCR</a>.<a id="93c15" class="tk">B</a>.<a id="93c17" class="tk">MSTR</a> = 1;              <span class="ct">/* SPI Mode,Master or Slave */</span></td></tr>
<tr name="94" id="94">
<td><a id="l94" class='ln'>94</a></td><td>  <a id="94c3" class="tk">DSPI</a>(1).<a id="94c11" class="tk">MCR</a>.<a id="94c15" class="tk">B</a>.<a id="94c17" class="tk">CONT_SCKE</a> = 0;</td></tr>
<tr name="95" id="95">
<td><a id="l95" class='ln'>95</a></td><td>  <a id="95c3" class="tk">DSPI</a>(1).<a id="95c11" class="tk">MCR</a>.<a id="95c15" class="tk">B</a>.<a id="95c17" class="tk">DCONF</a> = 0;</td></tr>
<tr name="96" id="96">
<td><a id="l96" class='ln'>96</a></td><td>                         <span class="ct">/* Configure DSPI_B in SPI, DSI or CSI configuration */</span></td></tr>
<tr name="97" id="97">
<td><a id="l97" class='ln'>97</a></td><td>  <a id="97c3" class="tk">DSPI</a>(1).<a id="97c11" class="tk">MCR</a>.<a id="97c15" class="tk">B</a>.<a id="97c17" class="tk">PCSIS</a> = 0<a id="97c26" class="tk">b11111111</a>;</td></tr>
<tr name="98" id="98">
<td><a id="l98" class='ln'>98</a></td><td>  <a id="98c3" class="tk">DSPI</a>(1).<a id="98c11" class="tk">MCR</a>.<a id="98c15" class="tk">B</a>.<a id="98c17" class="tk">MDIS</a> = <a id="98c24" class="tk">!</a>1;             <span class="ct">/* SPI Moudle enable */</span></td></tr>
<tr name="99" id="99">
<td><a id="l99" class='ln'>99</a></td><td>  <a id="99c3" class="tk">DSPI</a>(1).<a id="99c11" class="tk">MCR</a>.<a id="99c15" class="tk">B</a>.<a id="99c17" class="tk">HALT</a> = 1;              <span class="ct">/* Stop transfer */</span></td></tr>
<tr name="100" id="100">
<td><a id="l100" class='ln'>100</a></td><td>  <a id="100c3" class="tk">DSPI</a>(1).<a id="100c11" class="tk">MODE</a>.<a id="100c16" class="tk">CTAR</a>[0].<a id="100c24" class="tk">B</a>.<a id="100c26" class="tk">DBR</a> = <a id="100c32" class="tk">DBR0</a>;   <span class="ct">/* Duty cycle is configurable*/</span></td></tr>
<tr name="101" id="101">
<td><a id="l101" class='ln'>101</a></td><td>  <a id="101c3" class="tk">DSPI</a>(1).<a id="101c11" class="tk">MODE</a>.<a id="101c16" class="tk">CTAR</a>[0].<a id="101c24" class="tk">B</a>.<a id="101c26" class="tk">FMSZ</a> = 0<a id="101c34" class="tk">b1111</a>;<span class="ct">/* Frame size=16 */</span></td></tr>
<tr name="102" id="102">
<td><a id="l102" class='ln'>102</a></td><td>  <a id="102c3" class="tk">DSPI</a>(1).<a id="102c11" class="tk">MODE</a>.<a id="102c16" class="tk">CTAR</a>[0].<a id="102c24" class="tk">B</a>.<a id="102c26" class="tk">PCSSCK</a> = 0<a id="102c36" class="tk">b01</a>;<span class="ct">/* PCS to SCK delay scaler, 3 */</span></td></tr>
<tr name="103" id="103">
<td><a id="l103" class='ln'>103</a></td><td>  <a id="103c3" class="tk">DSPI</a>(1).<a id="103c11" class="tk">MODE</a>.<a id="103c16" class="tk">CTAR</a>[0].<a id="103c24" class="tk">B</a>.<a id="103c26" class="tk">CSSCK</a> = 0<a id="103c35" class="tk">b0100</a>;<span class="ct">/* PCS to SCK delay scaler, 32 */</span></td></tr>
<tr name="104" id="104">
<td><a id="l104" class='ln'>104</a></td><td>  <a id="104c3" class="tk">DSPI</a>(1).<a id="104c11" class="tk">MODE</a>.<a id="104c16" class="tk">CTAR</a>[0].<a id="104c24" class="tk">B</a>.<a id="104c26" class="tk">ASC</a> = 0<a id="104c33" class="tk">b0100</a>; <span class="ct">/* After SCK delay scaler */</span></td></tr>
<tr name="105" id="105">
<td><a id="l105" class='ln'>105</a></td><td>  <a id="105c3" class="tk">DSPI</a>(1).<a id="105c11" class="tk">MODE</a>.<a id="105c16" class="tk">CTAR</a>[0].<a id="105c24" class="tk">B</a>.<a id="105c26" class="tk">DT</a> = 0<a id="105c32" class="tk">b0100</a>;  <span class="ct">/* Delay after transfer scaler */</span></td></tr>
<tr name="106" id="106">
<td><a id="l106" class='ln'>106</a></td><td>  <a id="106c3" class="tk">DSPI</a>(1).<a id="106c11" class="tk">MODE</a>.<a id="106c16" class="tk">CTAR</a>[0].<a id="106c24" class="tk">B</a>.<a id="106c26" class="tk">CPOL</a> = 0;</td></tr>
<tr name="107" id="107">
<td><a id="l107" class='ln'>107</a></td><td>    <span class="ct">/* Clock polarity, 0 means the inactive state of SCK is low, 1 means high */</span></td></tr>
<tr name="108" id="108">
<td><a id="l108" class='ln'>108</a></td><td>  <a id="108c3" class="tk">DSPI</a>(1).<a id="108c11" class="tk">MODE</a>.<a id="108c16" class="tk">CTAR</a>[0].<a id="108c24" class="tk">B</a>.<a id="108c26" class="tk">CPHA</a> = 1;</td></tr>
<tr name="109" id="109">
<td><a id="l109" class='ln'>109</a></td><td>          <span class="ct">/* Clock phase, 0 means data is captured on the leading edge of SCK */</span></td></tr>
<tr name="110" id="110">
<td><a id="l110" class='ln'>110</a></td><td>  <a id="110c3" class="tk">DSPI</a>(1).<a id="110c11" class="tk">MODE</a>.<a id="110c16" class="tk">CTAR</a>[0].<a id="110c24" class="tk">B</a>.<a id="110c26" class="tk">LSBFE</a> = 0;</td></tr>
<tr name="111" id="111">
<td><a id="l111" class='ln'>111</a></td><td>                              <span class="ct">/* LSB first enable, 0: MSB first; 1: LSB first */</span></td></tr>
<tr name="112" id="112">
<td><a id="l112" class='ln'>112</a></td><td>  <a id="112c3" class="tk">DSPI</a>(1).<a id="112c11" class="tk">MODE</a>.<a id="112c16" class="tk">CTAR</a>[0].<a id="112c24" class="tk">B</a>.<a id="112c26" class="tk">PBR</a> = 0;      <span class="ct">/* Baud rate prescaler */</span></td></tr>
<tr name="113" id="113">
<td><a id="l113" class='ln'>113</a></td><td>  <a id="113c3" class="tk">DSPI</a>(1).<a id="113c11" class="tk">MODE</a>.<a id="113c16" class="tk">CTAR</a>[0].<a id="113c24" class="tk">B</a>.<a id="113c26" class="tk">BR</a> = 3;       <span class="ct">/* Baud rate scaler */</span></td></tr>
<tr name="114" id="114">
<td><a id="l114" class='ln'>114</a></td><td>  <a id="114c3" class="tk">DSPI</a>(1).<a id="114c11" class="tk">MCR</a>.<a id="114c15" class="tk">B</a>.<a id="114c17" class="tk">HALT</a> = 0;              <span class="ct">/* Start transfer */</span></td></tr>
<tr name="115" id="115">
<td><a id="l115" class='ln'>115</a></td><td><span class="br">}</span></td></tr>
<tr name="116" id="116">
<td><a id="l116" class='ln'>116</a></td><td></td></tr>
<tr name="117" id="117">
<td><a id="l117" class='ln'>117</a></td><td><span class="pp">#endif</span></td></tr>
<tr name="118" id="118">
<td><a id="l118" class='ln'>118</a></td><td></td></tr>
<tr name="119" id="119">
<td><a id="l119" class='ln'>119</a></td><td><span class="pp">#if</span> (<a id="119c6" class="tk">SPIAENABLE</a><a id="119c16" class="tk">||</a><a id="119c18" class="tk">SPIBENABLE</a>)</td></tr>
<tr name="120" id="120">
<td><a id="l120" class='ln'>120</a></td><td></td></tr>
<tr name="121" id="121">
<td><a id="l121" class='ln'>121</a></td><td><span class="ct">/**************************************************************************</span></td></tr>
<tr name="122" id="122">
<td><a id="l122" class='ln'>122</a></td><td><span class="ct"> * FUNCTION :    ec_spi_masterwriteread                                    *</span></td></tr>
<tr name="123" id="123">
<td><a id="l123" class='ln'>123</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="124" id="124">
<td><a id="l124" class='ln'>124</a></td><td><span class="ct"> * DESCRIPTION : SPI function in master mode                               *</span></td></tr>
<tr name="125" id="125">
<td><a id="l125" class='ln'>125</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="126" id="126">
<td><a id="l126" class='ln'>126</a></td><td><span class="ct"> * PARAMETERS :  -DSPIn: can be DSPI0, or DSPI1                 *</span></td></tr>
<tr name="127" id="127">
<td><a id="l127" class='ln'>127</a></td><td><span class="ct"> *               -PCSn: can be PCS_0, PCS_1, PCS_2, PCS_3, PCS_4, PCS_5    *</span></td></tr>
<tr name="128" id="128">
<td><a id="l128" class='ln'>128</a></td><td><span class="ct"> *               -Length: the number of data to be transmitted or received *</span></td></tr>
<tr name="129" id="129">
<td><a id="l129" class='ln'>129</a></td><td><span class="ct"> *               -Tx_Buffer: a pointer pointing to the buffer used to save *</span></td></tr>
<tr name="130" id="130">
<td><a id="l130" class='ln'>130</a></td><td><span class="ct"> *                the data transmitted by SPI                              *</span></td></tr>
<tr name="131" id="131">
<td><a id="l131" class='ln'>131</a></td><td><span class="ct"> *               -Rx_Buffer: a pointer pointing to the buffer used to save *</span></td></tr>
<tr name="132" id="132">
<td><a id="l132" class='ln'>132</a></td><td><span class="ct"> *                the data received by SPI                                 *</span></td></tr>
<tr name="133" id="133">
<td><a id="l133" class='ln'>133</a></td><td><span class="ct"> *                                                                         *</span></td></tr>
<tr name="134" id="134">
<td><a id="l134" class='ln'>134</a></td><td><span class="ct"> * RETURN:       None                                                      *</span></td></tr>
<tr name="135" id="135">
<td><a id="l135" class='ln'>135</a></td><td><span class="ct"> ***************************************************************************/</span></td></tr>
<tr name="136" id="136">
<td><a id="l136" class='ln'>136</a></td><td><span class="kw">void</span> <a id="136c6" class="tk">ec_spi_masterwriteread</a>(<a id="136c29" class="tk">uint8</a> <a id="136c35" class="tk">DSPIn</a>,<a id="136c41" class="tk">uint8</a> <a id="136c47" class="tk">PCSn</a>,<a id="136c52" class="tk">uint8</a> <a id="136c58" class="tk">Length</a>, <a id="136c66" class="tk">uint16</a></td></tr>
<tr name="137" id="137">
<td><a id="l137" class='ln'>137</a></td><td>  <a id="137c3" class="tk">Tx_Buffer</a>[], <a id="137c16" class="tk">uint16</a> <a id="137c23" class="tk">Rx_Buffer</a>[])</td></tr>
<tr name="138" id="138">
<td><a id="l138" class='ln'>138</a></td><td><span class="br">{</span></td></tr>
<tr name="139" id="139">
<td><a id="l139" class='ln'>139</a></td><td>  <a id="139c3" class="tk">uint8</a> <a id="139c9" class="tk">i</a> = 0;</td></tr>
<tr name="140" id="140">
<td><a id="l140" class='ln'>140</a></td><td>  <span class="kw">for</span> (<a id="140c8" class="tk">i</a>=0; <a id="140c13" class="tk">i</a><a id="140c14" class="tk">&lt;</a><a id="140c15" class="tk">Length</a>; <a id="140c23" class="tk">i</a><a id="140c24" class="tk">++</a>)             <span class="ct">/* Transmit all SPI data frame */</span></td></tr>
<tr name="141" id="141">
<td><a id="l141" class='ln'>141</a></td><td>  <span class="br">{</span></td></tr>
<tr name="142" id="142">
<td><a id="l142" class='ln'>142</a></td><td>    <span class="kw">switch</span> (<a id="142c13" class="tk">PCSn</a>)                  <span class="ct">/* Select PS accrording to hardware config */</span></td></tr>
<tr name="143" id="143">
<td><a id="l143" class='ln'>143</a></td><td>    <span class="br">{</span></td></tr>
<tr name="144" id="144">
<td><a id="l144" class='ln'>144</a></td><td>     <span class="kw">case</span>(<a id="144c11" class="tk">PCS_0</a>)<a id="144c17" class="tk">:</a></td></tr>
<tr name="145" id="145">
<td><a id="l145" class='ln'>145</a></td><td>      <a id="145c7" class="tk">DSPI</a>(<a id="145c12" class="tk">DSPIn</a>).<a id="145c19" class="tk">PUSHR</a>.<a id="145c25" class="tk">PUSHR</a>.<a id="145c31" class="tk">R</a> = (<a id="145c36" class="tk">uint32</a>)(0x08010000<a id="145c54" class="tk">|</a>(<a id="145c56" class="tk">uint16</a>)<a id="145c63" class="tk">Tx_Buffer</a>[<a id="145c73" class="tk">i</a>]);</td></tr>
<tr name="146" id="146">
<td><a id="l146" class='ln'>146</a></td><td>      <span class="kw">break</span>;</td></tr>
<tr name="147" id="147">
<td><a id="l147" class='ln'>147</a></td><td></td></tr>
<tr name="148" id="148">
<td><a id="l148" class='ln'>148</a></td><td>     <span class="kw">case</span>(<a id="148c11" class="tk">PCS_1</a>)<a id="148c17" class="tk">:</a></td></tr>
<tr name="149" id="149">
<td><a id="l149" class='ln'>149</a></td><td>      <a id="149c7" class="tk">DSPI</a>(<a id="149c12" class="tk">DSPIn</a>).<a id="149c19" class="tk">PUSHR</a>.<a id="149c25" class="tk">PUSHR</a>.<a id="149c31" class="tk">R</a> = (<a id="149c36" class="tk">uint32</a>)(0x08020000<a id="149c54" class="tk">|</a>(<a id="149c56" class="tk">uint16</a>)<a id="149c63" class="tk">Tx_Buffer</a>[<a id="149c73" class="tk">i</a>]);</td></tr>
<tr name="150" id="150">
<td><a id="l150" class='ln'>150</a></td><td>      <span class="kw">break</span>;</td></tr>
<tr name="151" id="151">
<td><a id="l151" class='ln'>151</a></td><td></td></tr>
<tr name="152" id="152">
<td><a id="l152" class='ln'>152</a></td><td>     <span class="kw">case</span>(<a id="152c11" class="tk">PCS_2</a>)<a id="152c17" class="tk">:</a></td></tr>
<tr name="153" id="153">
<td><a id="l153" class='ln'>153</a></td><td>      <a id="153c7" class="tk">DSPI</a>(<a id="153c12" class="tk">DSPIn</a>).<a id="153c19" class="tk">PUSHR</a>.<a id="153c25" class="tk">PUSHR</a>.<a id="153c31" class="tk">R</a> = (<a id="153c36" class="tk">uint32</a>)(0x08040000<a id="153c54" class="tk">|</a>(<a id="153c56" class="tk">uint16</a>)<a id="153c63" class="tk">Tx_Buffer</a>[<a id="153c73" class="tk">i</a>]);</td></tr>
<tr name="154" id="154">
<td><a id="l154" class='ln'>154</a></td><td>      <span class="kw">break</span>;</td></tr>
<tr name="155" id="155">
<td><a id="l155" class='ln'>155</a></td><td></td></tr>
<tr name="156" id="156">
<td><a id="l156" class='ln'>156</a></td><td>     <span class="kw">case</span>(<a id="156c11" class="tk">PCS_3</a>)<a id="156c17" class="tk">:</a></td></tr>
<tr name="157" id="157">
<td><a id="l157" class='ln'>157</a></td><td>      <a id="157c7" class="tk">DSPI</a>(<a id="157c12" class="tk">DSPIn</a>).<a id="157c19" class="tk">PUSHR</a>.<a id="157c25" class="tk">PUSHR</a>.<a id="157c31" class="tk">R</a> = (<a id="157c36" class="tk">uint32</a>)(0x08080000<a id="157c54" class="tk">|</a>(<a id="157c56" class="tk">uint16</a>)<a id="157c63" class="tk">Tx_Buffer</a>[<a id="157c73" class="tk">i</a>]);</td></tr>
<tr name="158" id="158">
<td><a id="l158" class='ln'>158</a></td><td>      <span class="kw">break</span>;</td></tr>
<tr name="159" id="159">
<td><a id="l159" class='ln'>159</a></td><td></td></tr>
<tr name="160" id="160">
<td><a id="l160" class='ln'>160</a></td><td>     <span class="kw">case</span>(<a id="160c11" class="tk">PCS_4</a>)<a id="160c17" class="tk">:</a></td></tr>
<tr name="161" id="161">
<td><a id="l161" class='ln'>161</a></td><td>      <a id="161c7" class="tk">DSPI</a>(<a id="161c12" class="tk">DSPIn</a>).<a id="161c19" class="tk">PUSHR</a>.<a id="161c25" class="tk">PUSHR</a>.<a id="161c31" class="tk">R</a> = (<a id="161c36" class="tk">uint32</a>)(0x08100000<a id="161c54" class="tk">|</a>(<a id="161c56" class="tk">uint16</a>)<a id="161c63" class="tk">Tx_Buffer</a>[<a id="161c73" class="tk">i</a>]);</td></tr>
<tr name="162" id="162">
<td><a id="l162" class='ln'>162</a></td><td>      <span class="kw">break</span>;</td></tr>
<tr name="163" id="163">
<td><a id="l163" class='ln'>163</a></td><td></td></tr>
<tr name="164" id="164">
<td><a id="l164" class='ln'>164</a></td><td>     <span class="kw">case</span>(<a id="164c11" class="tk">PCS_5</a>)<a id="164c17" class="tk">:</a></td></tr>
<tr name="165" id="165">
<td><a id="l165" class='ln'>165</a></td><td>      <a id="165c7" class="tk">DSPI</a>(<a id="165c12" class="tk">DSPIn</a>).<a id="165c19" class="tk">PUSHR</a>.<a id="165c25" class="tk">PUSHR</a>.<a id="165c31" class="tk">R</a> = (<a id="165c36" class="tk">uint32</a>)(0x08200000<a id="165c54" class="tk">|</a>(<a id="165c56" class="tk">uint16</a>)<a id="165c63" class="tk">Tx_Buffer</a>[<a id="165c73" class="tk">i</a>]);</td></tr>
<tr name="166" id="166">
<td><a id="l166" class='ln'>166</a></td><td>    <span class="br">}</span></td></tr>
<tr name="167" id="167">
<td><a id="l167" class='ln'>167</a></td><td></td></tr>
<tr name="168" id="168">
<td><a id="l168" class='ln'>168</a></td><td>    <a id="168c5" class="tk">ec_spi_delay</a>(<a id="168c18" class="tk">DSPIn</a>,100);</td></tr>
<tr name="169" id="169">
<td><a id="l169" class='ln'>169</a></td><td>             <span class="ct">/* Pop out of the delay function once the receive FIFO not empty */</span></td></tr>
<tr name="170" id="170">
<td><a id="l170" class='ln'>170</a></td><td>    <a id="170c5" class="tk">Rx_Buffer</a>[<a id="170c15" class="tk">i</a>] = (<a id="170c21" class="tk">uint16</a>)<a id="170c28" class="tk">DSPI</a>(<a id="170c33" class="tk">DSPIn</a>).<a id="170c40" class="tk">POPR</a>.<a id="170c45" class="tk">B</a>.<a id="170c47" class="tk">RXDATA</a>;</td></tr>
<tr name="171" id="171">
<td><a id="l171" class='ln'>171</a></td><td>    <a id="171c5" class="tk">DSPI</a>(<a id="171c10" class="tk">DSPIn</a>).<a id="171c17" class="tk">SR</a>.<a id="171c20" class="tk">R</a> = 0x90020000;</td></tr>
<tr name="172" id="172">
<td><a id="l172" class='ln'>172</a></td><td>  <span class="br">}</span></td></tr>
<tr name="173" id="173">
<td><a id="l173" class='ln'>173</a></td><td><span class="br">}</span></td></tr>
<tr name="174" id="174">
<td><a id="l174" class='ln'>174</a></td><td></td></tr>
<tr name="175" id="175">
<td><a id="l175" class='ln'>175</a></td><td><span class="pp">#endif</span></td></tr>
<tr name="176" id="176">
<td><a id="l176" class='ln'>176</a></td><td></td></tr>
<tr name="177" id="177">
<td><a id="l177" class='ln'>177</a></td><td><span class="ct">/* File trailer for ECUCoder generated file spi.c.</span></td></tr>
<tr name="178" id="178">
<td><a id="l178" class='ln'>178</a></td><td><span class="ct"> *</span></td></tr>
<tr name="179" id="179">
<td><a id="l179" class='ln'>179</a></td><td><span class="ct"> * [EOF]</span></td></tr>
<tr name="180" id="180">
<td><a id="l180" class='ln'>180</a></td><td><span class="ct"> */</span></td></tr>
<tr name="181" id="181">
<td><a id="l181" class='ln'>181</a></td><td></td></tr>
</table>
</pre>
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